Ethernet system

ABSTRACT

Four (4) unshielded twisted pairs of wires connect a hub and a computer in an Ethernet system: one (1) pair for transmission only, another for reception only and the other two (2) for transmission and reception. The signals in the wires are in packets each having timing signals defining a preamble and thereafter having digital signals representing information as by individual ones of three (3) amplitude levels. The signals received at the computer are provided with an automatic gain control (AGC) and then with digital conversions at a particular rate. A control loop operative upon the digital conversions regulates the AGC gain at a particular value. An equalizer operative only during the occurrence of the digital signals in each packet selects an individual one of the three (3) amplitude levels closest to the amplitude of each digital conversion at the time assumed to constitute the conversion peak. The amplitudes of the timing signals in each preamble at the times assumed to constitute the peaks and zero crossings of such signals are multiplied. The rate of such digital conversions is adjusted in accordance with the polarity and magnitude of the multiplication product. The relative amplitudes of the successive equalizer values following each preamble are evaluated at the times assumed to be the peaks of the digital conversions. The rate of the digital conversions is adjusted in accordance with such evaluations, thereby further regulating the digital conversions at the particular rate. The equalizer thus operates on the information signals in each packet at the signal peaks.

This invention relates to systems for, and methods of, operating in local area networks to provide for the transmission and reception of signals through unshielded twisted pairs of wires between a computer and a hub. The invention particularly relates to systems for, and methods of, using digital techniques for enhancing the recovery, and the quality of such recovery, of the digital signals passing through the unshielded twisted pairs to the computer so that the information represented by such digital signals can be restored at the computer.

Systems now exist for passing information between different computers in a local area network. The systems include a hub connected to computers located at spaced positions around the hub. The connections between the hub and each computer are generally through unshielded twisted pairs of wires. These wires are generally made from copper so that they have relatively large losses. This has limited the distance through which the signals can pass between the hub and each computer. The unshielded twisted pairs of wires have also limited the rate at which the signals can be transmitted. Until relatively recently, the distance between the hub and each computer has been limited to approximately one hundred (100 m.) and the rate of signal transmission has been limited to approximately 10 megabits per second (10 Mb/sec.).

The systems discussed in the previous paragraph and constituting the prior art have used analog techniques at the computer to recover the information represented by the digital signals. For example, the systems of the prior art have used analog equalizers to compensate for deteriorations in the characteristics of the digital signals as the digital signals pass through the unshielded twisted pairs of wires. These analog techniques have been satisfactory when the signals have passed through the unshielded twisted pairs of wires at a frequency of ten megabits per second (10 Mb/sec.)

The amount of information being transmitted through the unshielded twisted pairs of lines has been increasing at a relatively rapid rate. To provide for this increased transmission of information, the rate of transmission has been increased to one hundred megabits per second (100 Mb/sec.). The increased rate of signal transmission has prevented analog equalizers from operating effectively in restoring at the computer the signals transmitted from the hub.

Digital circuits have been considered for use in systems employing unshielded twisted pairs of wires and transmitting signals at one hundred megabits per second (100 Mb/sec) through distances as great as one hundred meters (100 m.). For example, digital adaptive equalization technology has been considered for such systems. However, such digital systems have been rejected for several reasons. One reason has been that the systems considered have not provided significantly enhanced performance. Furthermore, the complexity of such systems has been quite high, particularly in relation to any enhanced performance obtained from such systems. The cost of such digital systems has also been considered to be excessive.

This invention provides a system for, and method of, receiving at a computer packets of digital signals transmitted from a hub displaced by a distance of as much as one hundred meters (100 m.) from the computer and for recovering the information represented by the digital signals in the packets. The system and method of this invention provide for such recovery whether the digital signals are transmitted through the wires at a, frequency of ten megabits per second (10 Mb/sec.) or one hundred megabits per second (100 Mb/sec).

The system of this invention includes a digital adaptive equalizer for recovering the information represented by the digital signals in the packets. This equalizer is of an advanced design and includes feedback techniques to enhance the resolution provided by the equalizer in determining the amplitude level of each of the digital signals in each packet. The system and method of this invention are particularly adapted to operate with four (4) unshielded twisted pairs of wires, three (3) of the four (4) transmitting information whether the transmission is from the hub to the computer or from the computer to the hub. The system and method of this invention also include circuits and techniques for synchronizing the operation of the equalizer with the digital signals in the packets to enhance the recovery of the amplitudes of the digital signals by the equalizer.

In one embodiment of the invention, four (4) unshielded twisted pairs of wires connect a hub and a computer in an Ethernet system: one (1) pair of transmission only, another for reception only and the other two (2) for transmission and reception. The signals in the wires are in packets each having timing signals defining a preamble and thereafter having digital signals representing information as by individual ones of three (3) amplitude levels.

The signals received at the computer are provided with an automatic gain control (AGC) and then with digital conversion at a particular rate. A control loop operative upon the digital conversions regulates the AGC gain at a particular value. An equalizer operative only during the occurrence of the digital signals in each packet selects an individual one of the three (3) amplitude levels closest to the amplitude of each digital conversion at the time assumed to constitute the conversion peak.

The amplitudes of the timing signals in each preamble at the times assumed to constitute the peaks and zero crossings of such signals are multiplied. The rate of such digital conversions is adjusted in accordance with the polarity and magnitude of the multiplication product. The relative amplitudes of the successive equalizer values following each preamble are evaluated at the times assumed to be the peaks of the digital conversions. The rate of the digital conversions is adjusted in accordance with such evaluations, thereby further regulating the digital conversions at the particular rate. The equalizer thus operates on the information signals in each packet at the signal peaks.

In the drawings:

FIG. 1 is a schematic block diagram of an Ethernet system providing a plurality of computers connected to a hub by unshielded twisted pairs of wires to form a local area network (LAN);

FIG. 2 is a circuit diagram in block form of an overview of the hub and one of the computers in FIG. 1, the circuit diagram showing such computer and such hub, and connections of the unshielded twisted pairs of wires between them, when the computer receives packets of signals from the hub or transmits packet of signals to the hub;

FIG. 3 is a circuit diagram showing in block form the construction of the computer, and the unshielded twisted pairs of wires connected to the computer, when the computer operates to send packets of signals through the unshielded twisted pairs of wires to the hub;

FIG. 4 is a circuit diagram showing in block form the construction of the computer, and the connections of the unshielded twisted pairs of wires to the computer, when the computer operates to receive and decode packets of signals passing through the unshielded twisted pairs of wires from the hub;

FIG. 5 shows the relationship of timing signals in a preamble in each packet and of digital signals following the preamble and representing information or data, the packets being shown in three (3) different channels;

FIG. 6 is a circuit diagram in block form of the stages at a computer for transmitting or receiving signals in a packet, the circuit diagram including stages in the receiver unique to this invention;

FIG. 7 is a circuit diagram in block form of stages included in the receiver at the computer and unique to this invention;

FIG. 8 is a curve illustrating the operation of a digital adaptive equalizer included in the circuit diagram shown in FIG. 7;

FIG. 9 shows, curves of different patterns of successive digital signals in the packets when the digital signals have individual ones of the three (3) amplitude levels and have a frequency of twenty five megahertz (25 MHz);

FIGS. 10( a), 10(b) and 10(c) respectively show the progressive deterioration, at distances of thirty meters (30 m.), sixty meters (60 m.) and one hundred meters (100 m.) along an unshielded twisted pair of wires, of the digital signals following the preamble in each packet and representing information or data;

FIG. 11 is a circuit diagram showing in additional detail the system shown in FIG. 7 with particular emphasis on the construction of a block designated as “timing recovery” in FIG. 7;

FIGS. 12( a) and 12(b) show curves indicating the relative times of occurrence of the timing signals in the preamble in each packet when relatively small phase corrections have to be made in an analog-to-digital (A-D) converter shown in FIGS. 7 and 11;

FIG. 13( a)-13(d) show curves indicating the relative times of occurrence of the timing signals in the preamble in each packet when relatively small and large phase corrections have to be made in the analog-to-digital (A-D) converter shown in FIGS. 7 and 11;

FIG. 14 shows curves indicating the relative times of occurrence of successive ones of the digital signals following the preamble in each packet when corrections have to be made in the A-D converter to compensate for jitters that may occur in the digital conversions from the A-D converter;

FIG. 15 is a circuit diagram in block form of a loop filter shown in FIG. 11 and shows the construction of the loop filter in additional detail; and

FIG. 16 is a circuit diagram in block form of some of the stages in FIG. 11 and also shows the inter-relationship between these stages and a ring oscillator which adjusts the phase of the digital conversions from the A-D converter shown in FIGS. 7 and 11.

An Ethernet system incorporating the features of this invention is generally indicated at 10 in FIG. 1. The Ethernet system 10 includes a hub 12 and a plurality of computers serviced by the hub in a local area network (LAN). Four computers 14, 16, 18 and 20 are shown by way of illustration but a different number of computers may be used without departing from the scope of the invention. Each of the computers 14, 16, 18 and 20 may be displaced from the hub 12 by a distance as great as approximately one hundred meters (100 m.). The computers 14, 16, 18 and 20 are also displaced from each other. The Ethernet system is known in the prior art.

The hub 12 is connected to each of the computers 14, 16, 18 and 20 by unshielded twisted pairs of wires or cables. Generally, the wires or cables are formed from copper. Four (4) unshielded twisted pairs of wires are provided in the system 10 between each computer and the hub 12. For example, four (4) unshielded twisted pairs of wires 22 are provided between the hub 12 and the computer 14. The system shown in FIG. 1 is operative with several categories of twisted pair cables designated as categories 3, 4 and 5 in the telecommunications industry. Category 3 cables are the poorest quality (and lowest cost) and category 5 cables are the best quality (and highest cost).

FIG. 2 provides an overview on a simplified basis of a system, generally indicated at 24, in which the features of this invention are incorporated. The system 24 as shown in FIG. 2 is known in the prior art. The system 24 provides for a transmission of digital signals between one of the computers (e.g. the computer 14) and the hub 12 and the reception of such signals at the other of the computer and the hub. A similar system can be provided for each of the computers 16, 18 and 20. The system includes four (4) unshielded twisted pairs (UTP) 22, 26, 28 and 30 of wires or cables.

An amplifier 32 at the computer 14 and an amplifier 34 at the hub 12 are connected to transmit digital signals through the unshielded twisted pairs 22 of wires only in the direction from the computer 14 to the hub 12. An amplifier 36 at the hub 12 and an amplifier 38 at the computer 14 are connected to transmit digital signals through the unshielded twisted pair 26 of wires only from the hub 12 to the computer 14.

Each of the unshielded twisted pairs 28 and 30 of wires or cables is connected to pass signals from the hub 12 to the computer 14 and also from the computer to the hub. This results from the connections of amplifiers 40 and 42 in opposite directions in the computer 14 to the unshielded twisted pairs 28 of wires or cables and from the connections of amplifiers 44 and 46 in opposite directions in the hub 12 to such unshielded twisted pairs of wires. Similar connections are made to the unshielded twisted pairs 30 of wires.

FIG. 3 provides an overview of the computer 14 when the computer operates as a transmitter. This overview is known in the art. It will be appreciated that similar overviews may be provided for each of the computers 16, 18 and 20 when these computers operate as transmitters. As shown in FIG. 3, the computer 14 includes a media access controller 50. The controller 50 becomes operative when the computer 14 is simultaneously attempting to transmit and receive packets of signals. At such a time, the controller 50 provides a selective priority to the signals being received or to the signals being transmitted. Preferably the priority may be to the packets of signals being received since these packets of signals may otherwise be lost.

The signals to be transmitted are introduced to an encoder 52 which encodes each of the signals to one (1) of three (3) amplitude levels dependent upon the information represented by such signal. The encoding of the signals to the individual ones of the three (3) amplitude levels effectively provides a reduction in the frequency of the signals. The signals then pass to a data splitter 53 which operates as a demultiplexer to pass the signals in successive packets into successive ones of three (3) channels on a cyclic basis. This causes the frequency of the signals in the packets in each of the channels to be reduced to one third (⅓) of the frequency of the packets of signals from the encoder 52.

One of the three (3) channels in FIG. 3 includes stages 54 for shaping the waves of the transmitted signals and also includes a filter/coupler 56 for limiting the frequency of the signals and for coupling the filtered signals to an unshielded twisted pair (UTP) 58 (designated as Pair 1) of wires. Each of the other two channels also includes wave shaping stages and filter/couplers respectively corresponding to the stages 54 and 56 in FIG. 3. These stages respectively introduce signals to unshielded twisted pairs 60 (designated as Pair 3) and 62 (designated as Pair 4).

In addition to passing through the unshielded twisted pairs 60 and 62 of wires on cables, the signals received by the computer 14 pass through an unshielded twisted pair 64 (designated as Pair 2), a filter/coupler 66 and a carrier sensor 68 to the media access controller 50 to activate the media access controller when a collision in the computer 14 between transmitted and received signals is about to occur.

FIG. 4 provides an overview of the computer 14 when the computer operates as a receiver. This overview is known in the art. It will be appreciated that similar overviews may be provided for each of the computers 16, 18 and 20 when these computers operate as receivers. As shown in FIG. 4, the packets of signals are received on the unshielded twisted pairs 64 (Pair 2), 60 (Pair 3) and 62 (Pair 4) of wires. The packets of signals on the unshielded twisted pair 64 of wires are introduced to the filter/coupler 66 and then to the data recovery stage 68 which recovers the individual one of the three amplitude levels provided for each signal in each packet. The stages 64 and 66 are also shown in FIG. 3. A filter/coupler and a data recovery stage are also provided for each of the channels respectively associated with the unshielded twisted pairs 60 and 62 of wires.

The signals from the data recovery stage 68 and the other two (2) data recovery stages are introduced to a data combiner 70 which acts as a multiplexer to recombine the signals in the three (3) received channels. A decoder 72 then recovers the information represented by the individual ones of the three (3) amplitude levels for the successive signals in the packets. The decoded signals then pass to the media access controller 50 also shown in FIG. 3.

As previously described, the signals in the unshielded twisted pairs 58, 60, 62 and 64 of wires or cables have a data rate of one hundred megabits per second (100 Mb/sec.). The rate of the transmission of such signals is at twenty five megabauds per second (25 Mbaud/sec.). The signals are in packets each having signals identifying the beginning of such packet and each having, after such identifying signals, a plurality of timing signals at the beginning of such packet.

The timing signals are provided in preambles in the packets. There may illustratively be eighteen (18) timing signals in each packet. Each of the timing signals have two (2) amplitude levels (positive and negative). The timing signals for the different packets are respectively illustrated at 76 a, 76 b and 76 c in FIG. 5 for the channels 64 (Pair 2), 60 (Pair 3) and 62 (Pair 4). The timing signals are provided in preambles in the packets. The timing signals in each packet are followed by digital signals representing information or data. The digital signals in each packet have individual ones of three (3) amplitude levels to represent the information or data.

Although the digital signals representing the data in the packets have a frequency of one hundred megabits (100 Mb/sec.) per second, this frequency is reduced by the encoder 52 as a result of the conversion of the signals to three (3) amplitude levels. The frequency of such digital signals is also reduced by the data splitter 53 in FIG. 3 as previously described. The resultant digital signals in each of the unshielded twisted pairs 60, 62 and 64 of wires has a frequency of thirty three megabits per second (33 Mb/sec.).

FIG. 6 provides a simplified block diagram of a system constituting one embodiment of this invention for transmitting such signals from a computer such as the computer 14 through the unshielded twisted pairs of wires (e.g. the pairs 58, 60 and 62) to the hub and for receiving such signals through the unshielded twisted pairs (e.g. 60, 62 and 64) of wires at the computer from the hub and for processing such received signals at the computer to recover the information or data represented by such signals.

The system shown in FIG. 6 includes the media access controller 50 (also shown in FIGS. 3 and 4), a stage 80 (which constitutes a combination of the encoder 52 and the data splitter 53 in FIG. 3) and transmitters 82 a, 82 b and 82 c for passing the signals in the packets through the untwisted pairs 58 (Pair 1), 60 (Pair 3) and 62 (Pair 4) of wires or cables in FIG. 3. The signals received from the hub 12 pass through the untwisted pairs 64 (Pair 2), 60 (Pair 3) and 62 (Pair 4) of wires or cables in FIG. 4. These signals are respectively received by receivers and equalizers 84 a, 84 b and 84 c. The receivers and equalizers 84 a, 84 b and 84 c are included within the features of this invention. They operate on a digital basis to select the individual ones of the three (3) amplitude levels closest to the amplitudes of the received digital signals.

The signals from the receivers and equalizers 84 a, 84 b and 84 c pass to a clock recovery stage 86 which operates upon these signals to recover a clock signal. The stage 86 is included within the features of this invention. This clock signal is used to synchronize the operation of the receivers and equalizers 84 a, 84 b and 84 c and the data combiner and decoder 88. The clock signal from the stage 86 and the signals from the receivers and equalizers 84 a, 84 b and 84 c are introduced to a stage 88 which constitutes a combination of the data combiner (or multiplexer) 70 and the decoder 72 in FIG. 4. The combination of the stages 84 a, 84 b, 84 c, 86 and 88 is considered to be within the features of this invention. The signals from the stage 88 pass to the media access controller 50 also shown in FIGS. 3 and 4.

FIG. 7 illustrates one of three receiving and equalizing channels (see the receivers and equalizers 84 a, 84 and 84 c in FIG. 6) in the computer 14 in additional detail. It will be appreciated that each of the other two (2) receiving channels in the computer 14 may be constructed in a similar manner. The receiver and equalizer shown in FIG. 7 are unique to this invention. The receiver and equalizer shown in FIG. 7 include an automatic gain control stage (AGC) 90 which is connected to receive the signals passing through the unshielded twisted pair 64 of wires. The signals from the AGC stage 90 pass to an analog-to-digital (A-D) converter 92. The converter 92 provides digital conversions of the signals from the AGC stage 90 at a suitable frequency such as fifty megahertz (50 MHz), which is twice the baud rate of the signals.

The signals from the converter 92 pass to an AGC control loop 94. The signals from the AGC control loop 94 regulate the gain of the signals of the AGC stage 90 at a particular value. In this way, the amplitudes of the signals from the converter 92 are independent of any variation in the gain in the signals. The rate of production of the digital conversions is regulated by a timing recovery stage generally indicated at 96 so that the digital conversions of the signals from the stage 92 are at a particular rate and in a particular phase. The timing recovery stage 96 is shown in additional detail in subsequent Figures.

The output from the converter 92 is introduced to a digital adaptive equalizer generally indicated at 98 in FIG. 7. The stages in the digital adaptive equalizer 98 are shown within broken lines in FIG. 7. They include a feed forward equalizer 100 which is connected to the output of the A-D converter 92. A suitable feed forward equalizer for use as the equalizer 100 is disclosed in an article entitled “A 100 MHz, 5M Baud Decision Feedback Equalizer for Digital Television Applications” written by Robindra B. Joshi and Henry Samueli and published in the IEEE International Solid-States Circuits Conference on Feb. 16, 1994. The output of the feed forward equalizer 100 is introduced to an adder 102 as is the output from a decision feedback equalizer 104. The output from the adder 102 passes to a three (3)-level data slicer 106. The output from the data slicer 106 constitutes the input to the decision feedback equalizer 104. The output from the data slicer 106 also provides the data or information represented by the three (3)-level digital signals following the timing signals in the preamble in each packet. The output from the data slicer 106 is provided on a line 109.

The adder 102 adds the outputs of the feed forward equalizer 100 and the decision feedback equalizer 104 to provide an output which is introduced to the slicer 106. This addition may be seen from FIG. 8. As will be seen in FIG. 8, a composite signal generally indicated at 108 is shown as being comprised respectively of left and right halves 108 a and 108 b. The feed forward equalizer 100 may be considered to correct for distortions in the left half 108 a of the composite signal 108 and the decision feedback equalizer may be considered to correct for distortions in the right half 108 b of the composite signal 108. The distortions result in part from the fact that the digital signals representing information or data in each packet develop tails as they travel through the unshielded twisted pairs of wires. As a result of the corrections for these distortions, the adder 102 provides the value of the amplitude of the composite signal 108.

The output from the adder 102 is introduced to the slicer 106 in FIG. 7. The slicer 106 provides a plurality (e.g. 3) of progressive amplitude values and determines the particular one of the three (3) amplitude values closest to the output from the adder 102. The slicer 106 provides this value on the line 109 for each of the digital signals in each packet to indicate the data or information represented by such digital signals. In this way, the digital adaptive equalizer 98 restores the analog levels of the digital signals in the packets at the receiver to the analog levels of these digital signals at the hub 12 even with the distortions produced in these signals as they pass through the unshielded twisted pairs of wires.

FIG. 9 shows curves of different patterns of successive digital, signals in the packets when the digital signals have individual ones of the three (3) amplitude levels and have a frequency of twenty five megahertz (25 MHz). In FIG. 9, time in 10⁻⁸ seconds is shown along the horizontal axis and relative amplitudes in positive and negative polarities are shown along the vertical axis. For example, three successive amplitude levels of +1, +1 and +1 are indicated at 110 in FIG. 9 and three successive amplitude levels of −1, −1 and −1 are indicated at 112 in that Figure. Similarly, three (3) successive amplitude levels of 0, +1 and 0 are indicated at 114 in FIG. 9 and three (3) successive amplitudes of +1, 0 and +1 are indicated at 116 in that Figure. Three successive amplitude levels of 0, 0, 0 are also indicated at 118 in FIG. 9 and three successive amplitudes of +1, −1 and +1 are also indicated at 120 in FIG. 1. FIG. 9 represents the desired (or perfect) wave forms for different combinations of three (3) successive digital signals in a packet.

FIGS. 10( a), 10(b) and 10(c) show the degradations in the signal combinations of FIG. 9 after the signals in such combinations have travelled different distances between the hub 12 and the computer 14. FIG. 10( a) shows the degradations in such signal combinations after the signals in such combinations have travelled a distance of approximately thirty meters (30 m.) through one of the unshielded twisted pairs 64, 60 and 62 of wires.

FIG. 10( b) shows the further degradations in such signal combinations after the signals in such combinations have travelled a distance of approximately sixty meters (60 m.) through one of such unshielded twisted pairs of wires. The degradation in such signal combinations is further aggravated after the signals in such combinations have travelled a distance of approximately one hundred meters (100 m.) through one of the unshielded twisted pairs 64, 60 and 62 between the hub 12 and the computer 14.

This invention recovers in the computer 14 the pattern of the successive signals transmitted through each of the unshielded pairs 64, 60 and 62 of wires from the hub 12 even after such signals have travelled a distance of approximately one hundred meters (100 m.) from the hub and have suffered the degradation shown in FIG. 10( c). As will be seen, clearing up the signal confusion shown in FIG. 10 c to restore the signals shown in FIG. 9, as by the system of this invention, constitutes a significant achievement.

FIG. 11 is a circuit diagram showing in additional detail the system shown in FIG. 7 with particular emphasis on the construction of the timing recovery block 96 in FIG. 7. The system shown in FIG. 11 includes the A-D converter 90 and the equalizer 98 also shown in FIG. 7. The A-D converter 90 receives on a line 122 clock signals at the master clock frequency of fifty megahertz (50 MHz). The A-D converter provides outputs at the times assumed to be the peaks and zero crossings of the digital conversions from the converter 90. The outputs from the A-D converter 90 are used in the system shown in FIG. 11 to adjust the phase of the master clock frequency so that the signals will actually be produced at the peaks and zero crossings of the master clock signals. The output at the time assumed to be the peak of the digital conversions is designated as “x_(p)” in FIG. 11 and the output at the time assumed to be the zero crossing is designated as “x_(o)” in FIG. 11.

The signal x_(p) from the converter 90 is shown in FIG. 11 as being introduced to the equalizer 98. As previously described, the equalizer 98 operates upon the signal x_(p) to select the individual one of the three (3) amplitude levels closest in amplitude to the signal x_(p). This amplitude level is designated in FIG. 11 as “{circumflex over (x)}”. The signal {circumflex over (x)} from the equalizer 98 is introduced to a low gain error generator 124 which is included within the timing recovery block 96 also shown in FIG. 7. The stages included in the timing recovery block 96 are disposed within a rectangle shown in broken lines in FIG. 11. This recovery block is generally indicated at 96 in FIGS. 7 and 11. The low gain error generator 124 also receives the x_(o) output from the A-D converter 90 and provides an output, designated as a “low gain error”, on a line 125 to a loop filter generally indicated at 126 and included within the timing recovery block 96.

The loop filter 126 also receives clock signals on a line 128 at a baud clock rate of twenty five megahertz (25 MHz). The loop filter 126 additionally receives signals, designated as “boost & boost 2”, on a line 130 from a high gain error generator 132. Signals designated as “high gain error” are introduced on a line 134 from the high gain error generator 132 to the loop filter 126. A phase inverter 136 provides signals (designated as “freeze”) on a line 138 to the loop filter 126. The output from the loop filter 126 passes through a line 140 to a ring oscillator generally indicated at 186 shown in additional detail in FIG. 16.

The phase inverter 136 receives the clock signals on the line 122 at the master clock frequency of fifty megahertz (50 MHz) and clock signals at the baud clock frequency of twenty five megahertz (25 MHz). The clock signals on the line 128 also pass to internal blocks. The clock signals on the lines 122 and 128 also pass to a controller 142. The controller 142 also receives on a line 144 signals which indicate the start of each packet. These signals are provided in a special pattern at the beginning of each packet. The controller 142 provides other control signals on a line 146.

The signals x_(p) and x_(o) at the times respectively assumed to be the peaks and zero crossings of the timing signals 76 a, 76 b and 76 c (FIG. 5) pass from the A-D converter 90 to the high gain error generator 132. FIG. 12 indicates the response of the high gain error generator 132 to the signals x_(p) and x_(o) generated during the occurrence of the timing signals in the preamble in each packet. The high gain error generator 132 multiplies the values of the signals x_(p) and x_(o) for each of the timing signals and determines from the multiplication product the correction, if any, which should be made in the times assumed for the peak x_(p) and the zero crossing x_(o) to occur.

When the product of x_(p) and x_(o) for a timing signal is zero, no correction has to be made since the time assumed by the baud clock signal on the line 128 to be the zero crossing for a timing signal is actually the time that the zero crossing has occurred. When the signal x_(p) occurs at a time indicated at 148 in FIG. 12( a) and the signal x_(o) occurs at a time indicated at 150 in FIG. 11( a), the product of x_(p) and x_(o) is positive. This indicates that the time assumed by the baud clock signal on the line 148 for the peak x_(p) and the zero crossing x_(o) to occur is early. As a result, the error generator 132 delays the phase of the baud clock signal on the line 128 in FIG. 11 so that the times assumed for the peak x_(p) and the zero crossing x_(o) to occur will approach the times that such peak x_(p) and such zero crossing x_(o) actually occur.

FIG. 11( b) provides another illustration of the times 152 a and 154 respectively assumed for the peak x_(p) and the zero crossing x_(o) to occur in one of the timing cycles in the preamble of a packet. As will be seen, since x_(o) has a negative polarity and x_(p) has a positive polarity, the polarity of the product of x_(p) and x_(o) is negative. This indicates that x_(p) and x_(o) are occurring at a late time. The phases of the baud clock signals are accordingly shifted in a leading direction so that the times assumed for x_(p) and x_(o) to occur approach the time that x_(p) and x_(o) actually occur.

FIGS. 13( a) and 13(b) respectively show the same relationship in time between x_(p) and x_(o) as shown in FIGS. 12( a) and 12(b). As will be seen in FIGS. 13( a) and 13(b) and also in FIGS. 12( a) and 12(b), a relatively small amount of a phase shift has to be made in the phase of the baud clock signals on the line 128 in FIG. 11 to bring the signal x_(p) in synchronism with the peak of the baud clock signals actually occurring on the line 128 and to bring the zero crossing x_(o) in synchronism with the zero crossing of the baud clock signals actually occurring on the line 128. This may be seen from the fact that |x_(p)|>K|x_(o)| in FIGS. 13( a) and 13(b) where K is a constant having a relatively high value greater than 1.

Sometimes, however, the baud clock signals on the line 128 are considerably out of synchronism with the signals x_(p) and x_(o) respectively assumed to constitute the peaks and zero crossings. This is shown in FIGS. 13( c) and 13(d). As will be seen in FIG. 13( c), the signals x_(p) and x_(o) are delayed relative to the baud clock signals on the line 128 by a phase angle approaching 90°. In FIG. 13( d), the signals x_(p) and x_(o) are delayed relative to the baud clock signals on the line 128 by a phase angle greater than 90°. In both of these instances, |x_(p)|<K|x_(o)|. In both of these situations, synchronization between the baud clock signals on the line 128 on the one hand and the peak signal x_(o) and the zero crossing signal x_(p) on the other hand will occur on an expedited basis when a phase shift (or phase inversion) of 90° is provided.

When the phase shift of 90° occurs in the time relationship shown in FIG. 13( c), the relative positions of the x_(p) and x_(o) signals in FIG. 13( c) will be shifted to the relative positions of these signals in FIG. 13( a). Similarly, the relative positions of the x_(p) and x_(o) signals in FIG. 13( d) will be shifted to the relative positions of these signals in FIG. 13( b) when a phase shift of 90° is provided in these signals. Relatively minor corrections can thereafter be provided in the phase of the clock signals to have x_(p) correspond to the peak of the baud clock signals on the line 128 and to have x_(o) correspond to the zero crossing of such baud clock signals.

The phase inverter 136 in FIG. 11 provides the phase shift of 90° discussed in the previous paragraph. The relationship shown in FIGS. 13( c) and 13(d) to create the phase inversion of 90° is advantageous because it minimizes false inversions resulting from large amplitudes of noise or from the trailing spikes that are produced as a result of the passage of the digital signals for a distance of one hundred meters (100 m.) through the unshielded twisted pair of wires.

Only one phase shift of 90° is provided during the preamble in each packet. This is indicated by the “freeze” indication on the line 138 in FIG. 11. The reason for this is that more than one such phase shift in a preamble will tend to create instability in the effort to synchronize the baud clock signal on the line 128 with the peak signal x_(p) and the zero crossing x_(o) during the occurrence of the timing signals in the preamble in each packet.

Furthermore, the phase shifts in the clock signals on the line 128 are made only during a first limited number of timing signals in each preamble. This results from the introduction of a signal (designated as “time out”) on a line 139 from the controller 142 to the phase inverter 136. For example, if there are eighteen (18) timing signals in each preamble, the phase shifts in the clock signals on the line 128 will preferably be made only in the first ten (10) timing signals in such preamble. This prevents large amplitudes of noise in the last eight (8) timing signals of a preamble from producing undesired phase shifts of 90° in the clock baud signals on the line 128. Such large phase shifts in the last timing signals in each preamble tend to create instabilities, particularly when such large phase shifts result from the introduction of noise into the system.

Sometimes the gain of the signals from the converter 90 is relatively low. When the gain of the converter 90 as represented by the x_(p) and x_(o) signals is at least fifty percent (50%) below the dynamic range of the converter 90, a signal is introduced on the line 130 to the loop filter 126. This causes the loop gain to be doubled. The loop gain is doubled again when the gain of the converter 90 as represented by the x_(p) and x_(o) signals is below twenty five percent (25%) of the dynamic range of the converter 90.

The low gain error generator 124 provides error corrections during the occurrence of the digital signals following the timing signals in the preamble of each packet. These digital signals indicate the data or information in each packet. As a result of these error corrections, the phase of the digital conversions by the A-D converter 90 is regulated so that the signal x_(o) occurs at the zero crossings of the digital signals following the preamble in the packet and the signal {circumflex over (x)} from the equalizer 98 represents the peak of such digital signals.

The low-gain error generator 124 provides such phase regulation by operating upon successive ones of the digital signals. This may be seen from FIG. 14. In FIG. 14, two successive indications from the equalizer 98 are indicated as {circumflex over (x)}₁ and {circumflex over (x)}₂. The zero crossing between the two (2) successive indications {circumflex over (x)}₁ and {circumflex over (x)}₂ is indicated as x_(o). The low gain error generator 124 in FIG. 11 adjusts the phase of the signals from the A-D converter 90 on the basis of the relative values of {circumflex over (x)}₁, x_(o) and {circumflex over (x)}₂ to eliminate any jitter in the phase of the digital signals from the A-D converter.

FIG. 14( a) indicates a situation where {circumflex over (x)}₁, x_(o) and {circumflex over (x)}₂ have no transition. Under such circumstances, no change is made in the phase of the signals produced by the A-D converter 90, particularly since it is difficult to determine what, if any, correction should be made. FIG. 14( b) indicates a situation where {circumflex over (x)}₁ is positive and {circumflex over (x)}₂ is negative and x_(o) occurs before the zero crossing. Under such circumstances, the zero crossing occurs early. A phase adjustment based upon K₃x_(o) is made in the signals from the A-D converter to delay the phase so that x_(o) will occur at the zero crossing. In the phase adjustment of K₃x_(o), K₃ is a constant. The value of K₃ is less than the value of the constant K for the situations shown in FIGS. 12( a) and 12(b) and described above.

FIGS. 14( c) and 14(d) indicate situations where x_(o) is late relative to the zero crossing. In FIG. 14( c), {circumflex over (x)}₁ is positive, x_(o) is negative and {circumflex over (x)}₂ is negative. In FIG. 14( d), {circumflex over (x)}₁ is negative, x_(o) is positive and {circumflex over (x)}₂ is positive. In the situations of both FIGS. 14( c) and 14(d), the A-D converter 90 delays the phase of the digital conversions produced by the A-D converter 90 so that x₀ will occur at the zero crossings. In both FIGS. 14( c) and 14(d), K₃ is the constant for advancing the phase of the digital conversions by the A-D converter 90.

As will be seen, FIGS. 14( b), 14(c) and 14(d) indicate transitions in {circumflex over (x)}₁ and {circumflex over (x)}₂ between positive and negative values. Such transitions are accordingly designated in FIG. 14 as “Full Transitions”. FIGS. 14( e), 14(f) and 14(g) indicate half transitions. In other words, {circumflex over (x)}_(i), x_(o) and {circumflex over (x)}₂ have progressive values between a peak and a zero crossing or between a zero crossing and a peak without changing polarity. The transitions in FIGS. 14( e), 14(f) and 14(g) are accordingly designated as “Half Transitions” in FIG. 14.

In FIG. 14( e), the transition is between a positive peak for {circumflex over (x)}_(i) and a zero value for {circumflex over (x)}₂. In FIG. 14( f), the transition is between a zero value for {circumflex over (x)}₁ and a positive peak for {circumflex over (x)}₂. In FIG. 14( g), the transition is between a negative peak for {circumflex over (x)}₁ and a zero value for {circumflex over (x)}₂. In each instance, the value of x_(o) is between the peak and the zero value.

Since only half transitions are involved in FIGS. 14( e), 14(f) and 14(g), a constant K₂ is chosen that is less than the constant K₃ for the change in the phase of the digital conversions from the A-D converter 90 as in FIG. 14( b) and FIG. 14( c). In FIG. 14( e), the digital conversion by the A-D converter 90 is early so that the phase of the digital conversion is delayed to have x_(o) occur at the zero crossing. In FIG. 14( f), the digital conversion by the phase detector 90 is late so that the phase of the digital conversion is advanced to have x_(o) occur at the zero crossing. Similarly, the digital conversion by the phase detector 90 is delayed in FIG. 14( g) to have x_(o) occur at the zero crossing.

The signals from the high gain error generator 132 and the low gain error generator 124 are introduced to the loop filter 126 shown as a block in FIG. 11. The loop filter 126 operates in synchronism with the baud clock signals of twenty five megahertz (25 MHz) on the line 128. The loop filter 126 is shown in additional detail, but on a block diagram basis, in FIG. 15. It includes a line 170 which is schematically intended to indicate, on a generic basis, any of the line 125 (FIG. 11) from the low gain error generator 124, the line 134 from the high gain error generator 132 or the line 138 from the phase inverter 136.

The signals on the line 170 in FIG. 15 are multiplied in an amplifier 172 which provides an amplification generically indicated at K_(G). The amplification factor K_(G) for the amplifier 172 may respectively be K₃ or K₂ if the signals on the line 170 are provided from the line 125 (FIG. 11) or the amplification factor May be K if the signals on the line 170 are provided from the line 134 in FIG. 11.

The signals from the amplifier 172 in FIG. 15 pass to an adder 174 which also receives signals from a register 176. The output from the adder 174 is introduced to the register 176. The output from the register 176 is introduced on the line 140 in FIGS. 11 and 15 to a ring oscillator in FIG. 16. The register 176 accumulates the signals from the amplifier 172 by the addition in the adder 174 of the signals from the amplifier and the register.

FIG. 16 shows the low gain error generator 124 and the high gain error generator which are also shown in FIG. 11. The signals from the error generators 124 and 132 are introduced in FIG. 16 to a select stage 180 which may constitute a multiplexer. The operation of the select stage 180 is controlled by signals on the line 146 (also shown in FIG. 11) from the controller 142 to indicate whether the signals in the packet at each instant are the timing signals in the preamble or the information or data signals following the preamble. The signals from the select stage 180 pas through the loop filter 126 (also shown in FIGS. 11 and 15) to a multiplexer 182, the output of which constitutes the baud clock signals on the line 128 (also shown in FIG. 11).

The multiplexer 182 receives the signals from a voltage controlled oscillator generally indicated at 186 and shown within broken lines in FIG. 16. The voltage controlled oscillator includes a plurality of amplifiers in a ring relationship. Preferably sixteen (16) amplifiers are included in the ring relationship but only eight (8) amplifiers 188 a, 188 b, 188 c, 188 d, 188 e, 188 f, 188 g and 188 h are shown in FIG. 16 since they provide differential outputs. The output of each amplifier in the sequence is connected to the input of the next output in the sequence and the output of the last amplifier 188 h in the sequence is connected to the input of the first oscillator 188 a in the sequence.

Each packet has signals in a unique pattern to indicate the beginning of the packet. The controller 142 (FIG. 11) senses this unique pattern of signals on the line 144 to indicate the beginning of the packet. The controller 142 then produces a signal on the line 146 (FIGS. 11 and 16) to indicate whether the signals in the packet are the timing signals in the preamble or the digital signals following the preamble and representing information or data.

When the signal on the line 146 indicates the occurrence of the timing signals, the signals from the high gain error generator 132 pass through the select stage and the loop filter 126 to the multiplexer 182. These signals activate the multiplexer 182 to pass the signals from one of the amplifiers 188 a-188 h. By selecting a different one of the amplifiers 188 a-188 h in each cycle phase is adjusted in accordance with the characteristics of the signals from the high gain error generator 132. The phase-adjusted clock signals are introduced to the A-D converter 90 to obtain the generation of the digital conversions by the converter.

Except for the instances where a phase inversion is provided, the phase adjustment in each cycle is limited to a particular magnitude. For example, when sixteen (16) amplifiers are provided in the ring oscillator 186, each phase adjustment may be limited to that provided by two (2) successive amplifiers in the ring oscillator 186. This enhances the stability in adjusting the phase of the clock signals on the line 128 so that the signal x_(o) occurs at the zero crossing of the clock signals.

When a phase inversion of 90° occurs, an adjustment in the phase of the clock signals on the line 128 in FIG. 11 is not made at the same time as a result of the operation of the high gain error generator 132. This enhances the stability in the phase adjustments. An adjustment in the phase of the clock signals is also not made during the time between the occurrence of the successive packets.

When the signal on the line 146 in FIGS. 11 and 16 indicates the occurrence of the digital signals representing the information or data in a packet, the select stage 180 passes a signal to the loop filter 126 to provide a gain of K₃ or K₂ in the loop filter depending upon the relative characteristics of the curve represented by {circumflex over (x)}₁, x_(o) and {circumflex over (x)}₂ in FIG. 14. The multiplexer 182 then selects one of the amplifiers 188 a-188 g for the passage of a signal to the clock line 128 in accordance with the operation of the loop filter 126.

Although this invention has been disclosed and illustrated with reference to particular embodiments, the principles involved are susceptible for use in numerous other embodiments which will be apparent to persons skilled in the art. The invention is, therefore, to be limited only as indicated by the scope of the appended claims. 

1-103. (canceled)
 104. Apparatus adapted to be coupled to at least a twisted first wire pair enabling receipt of at least first, second and third discrete analog signal levels with different amplitudes representing information, a twisted second wire pair enabling receipt of at least fourth, fifth and sixth discrete analog signal levels with different amplitudes representing information and a twisted third wire pair enabling receipt of at least seventh, eighth and ninth discrete analog signal levels with different amplitudes representing information, the analog signal levels being received one discrete signal level at a time, the apparatus comprising: an analog to digital converter arranged to convert the first discrete analog signal level to a corresponding digital first information signal, to convert the second discrete analog signal level to a corresponding digital second information signal, to convert the third discrete analog signal level to a corresponding digital third information signal, to convert the fourth analog signal level to a corresponding digital fourth information signal, to convert the fifth discrete analog signal level to a corresponding digital fifth information signal, to convert the sixth discrete analog signal level to a corresponding digital sixth information signal, to convert the seventh discrete analog signal level to a corresponding digital seventh information signal, to convert the eighth discrete analog signal level to a corresponding digital eighth information signal and to convert the ninth discrete analog signal level to a corresponding digital ninth information signal; and circuitry arranged to individually identify each of the first, second, third, fourth, fifth, sixth, seventh, eighth and ninth discrete analog signal levels, to shift in time the first information signal relative to the first discrete analog signal level, to shift in time the second information signal relative to the second discrete analog signal level, to shift in time the third information signal relative to the third discrete analog signal level, to shift in time the fourth information signal relative to the fourth discrete analog signal level, to shift in time the fifth information signal relative to the fifth discrete analog signal level, to shift in time the sixth information signal relative to the sixth discrete analog signal level, to shift in time the seventh information signal relative to the seventh discrete analog signal level, to shift in time the eighth information signal relative to the eighth discrete analog signal level and to shift in time the ninth information signal relative to the ninth discrete analog signal level.
 105. The apparatus of claim 104, wherein the analog to digital converter is arranged to convert the discrete analog signals levels to corresponding digital information signals at a particular rate and wherein the circuitry comprises a timing recovery circuit arranged to regulate the particular rate at which said analog to digital converter converts the discrete analog signal levels.
 106. The apparatus of claim 105, wherein the circuitry comprises a digital adaptive equalizer arranged to identify the discrete analog signal level being received on each of the wire pairs.
 107. The apparatus of claim 106, further comprising an automatic gain control circuit coupled to the analog to digital converter.
 108. The apparatus of claim 106, further comprising a decoder circuit coupled to the digital adaptive equalizer.
 109. The apparatus of claim 108, further comprising a media access controller coupled to said decoder circuit.
 110. The apparatus of claim 106, wherein the digital adaptive equalizer includes a feedforward equalizer, a data slicer and a decision feedback equalizer.
 111. The apparatus of claim 106, wherein said timing recovery circuit regulates the particular rate in accordance with a product of a plurality of signal samples.
 112. The apparatus of claim 104, further comprising a clock arranged to generate clock signals having a phase and wherein the analog to digital converter is arranged to convert the discrete analog signal levels to the corresponding digital information digital signals in response to the clock signals and wherein the circuitry is arranged to shift the phase of the clock signals so that the time at which the analog to digital converter samples the discrete analog signal levels is adjusted.
 113. The apparatus of claim 112, wherein the circuitry shifts the phase of the clock signals in accordance with a product of a plurality of signal samples.
 114. The apparatus of claim 112, wherein each of the wire pairs enables receipt of timing discrete analog signal levels, wherein the analog to digital converter is arranged to convert the timing discrete analog signal levels to corresponding timing digital signals in response to the clock signals, and wherein the circuitry is arranged to shift the phase of the clock signals in response to the timing digital signals.
 115. The apparatus of claim 114, wherein the circuitry is arranged to shift the phase of the clock signals in response to both the timing digital signals and the information digital signals.
 116. In apparatus adapted to be coupled to at least a twisted first wire pair enabling receipt of at least first, second and third discrete analog signal levels with different amplitudes representing information, a twisted second wire pair enabling receipt of at least fourth, fifth and sixth discrete analog signal levels with different amplitudes representing information and a twisted third wire pair enabling receipt of at least seventh, eighth and ninth discrete analog signal levels with different amplitudes representing information, the analog signal levels being received one discrete signal level at a time, a method of processing the received discrete analog signal levels comprising: converting the first discrete analog signal level to a corresponding digital first information signal; converting the second discrete analog signal level to a corresponding digital second information signal; converting the third discrete analog signal level to a corresponding digital third information signal; converting the fourth discrete analog signal level to a corresponding digital fourth information signal; converting the fifth discrete analog signal level to a corresponding digital fifth information signal; converting the sixth discrete analog signal level to a corresponding digital sixth information signal; converting the seventh discrete analog signal level to a corresponding digital seventh information signal; converting the eighth discrete analog signal level to a corresponding digital eighth information signal; converting the ninth discrete analog signal level to a corresponding digital ninth information signal; individually identifying each of the first, second, third, fourth, fifth, sixth, seventh, eighth and ninth discrete analog signal levels; shifting in time the first information signal relative to the first discrete analog signal level; shifting in time the second information signal relative to the second discrete analog signal level; shifting in time the third information signal relative to the third discrete analog signal level; shifting in time the fourth information signal relative to the fourth discrete analog signal level; shifting in time the fifth information signal relative to the fifth discrete analog signal level; shifting in time the sixth information signal relative to the sixth discrete analog signal level; shifting in time the seventh information signal relative to the seventh discrete analog signal level; shifting in time the eighth information signal relative to the eighth discrete analog signal level; and shifting in time the ninth information signal relative to the ninth discrete analog signal level.
 117. The method of claim 116, wherein each of the converting steps comprises converting one of the discrete analog signals levels to a corresponding one of the information signals at a particular rate and further comprising regulating the particular rate.
 118. The method of claim 117, wherein said regulating comprises regulating the particular rate in accordance with a product of a plurality of signal samples.
 119. The method of claim 116, further comprising controlling the gain of the each of the received discrete analog signal levels.
 120. The method of claim 116, further comprising decoding each of the digital information signals.
 121. The method of claim 116, further comprising controlling media access.
 122. The method of claim 116, further comprising generating clock signals having a phase and wherein each of the converting steps comprises converting one of the discrete analog signal levels to one of the corresponding digital information signals in response to the clock signals and wherein each of the shifting steps comprises shifting the phase of the clock signals so that the time at which the converting occurs is adjusted.
 123. The method of claim 122, wherein the shifting comprises shifting the phase of the clock signals in accordance with a product of a plurality of signal samples.
 124. The method of claim 122, wherein each of the wire pairs enables receipt of timing discrete analog signal levels, wherein the converting comprises converting the timing discrete analog signal levels to corresponding timing digital signals in response to the clock signals, and wherein the shifting comprises shifting the phase of the clock signals in response to the timing digital signals.
 125. The method of claim 124, wherein the shifting comprises shifting the phase of the clock signals in response to both the timing digital signals and the digital information signals.
 126. A communication system for decoding signals having three or more analog signal levels to represent information transmitted by a first computer over a plurality of pairs of twisted wires to a second computer, said communication system including a transceiver comprising: a plurality of receivers and transmitters operatively coupled to respective ones of said plurality of said pairs of twisted wires, wherein each of said plurality of receivers comprises: an analog to digital converter; an automatic gain control circuit; and a digital adaptive equalizer that includes a feed forward equalizer, a decision feedback equalizer and a data slicer, wherein each of said analog to digital converters sampling said analog signal at a sampling rate, each of said automatic gain control circuits receiving said analog signal from one of said pairs of twisted wires and providing gain control at the input to a respective one of said analog to digital converters, and each of said equalizers producing recovered digital data from said sampled analog signal provided at the input of said equalizer, and wherein said transceiver includes a plurality of transmitters that simultaneously transmit three or more analog signal levels to said first computer over said plurality of pairs of twisted wires.
 127. The system of claim 126, wherein said transceiver combines said recovered data from each of said digital adaptive equalizers into a single recovered digital data stream.
 128. The system of claim 127, wherein said single recovered data stream is Ethernet data.
 129. The system of claim 126, wherein said communication system is an Ethernet system.
 130. The system of claim 126, wherein the digital data is Ethernet data with a data rate of at least 100 Mbps.
 131. The system of claim 126, wherein each of said equalizer includes an adder that sums the output of respective ones of said decision feedback equalizers and said feed forward equalizers.
 132. The system of claim 131, wherein the digital data is Ethernet data.
 133. A computer network device, comprising: transmitting circuitry including an encoder and data splitter circuitry, a first transmitter, a second transmitter and a third transmitter, wherein the first transmitter, the second transmitter and the third transmitter are coupled to a network via a respective pair of twisted wires; receiving circuitry including clock recover circuitry, data combiner and decoder circuitry, a first receiver and equalizer, a second receiver and equalizer and a third receiver and equalizer, wherein the clock recover circuitry is disposed along a data path between the receivers and equalizers and the data combiner and decoder circuitry, wherein the first receiver and equalizer, the second receiver and equalizer and the third receiver and equalizer is coupled to the network via a respective pair of twisted wires; a media access control coupled to a system bus, the encoder and data splitter circuitry of the transmitting circuitry and the data combiner and decoder circuitry of the receiver circuitry; and collision detect and link control circuitry coupled to the media access control, the transmitters and the receivers and equalizers, wherein the first receiver and equalizer comprises an automatic gain control stage, an analog-to-digital converter and a digital adaptive equalizer, wherein the automatic gain control state is coupled to the analog-to-digital converter, and wherein the analog-to-digital converter is coupled to the digital adaptive equalizer.
 134. The computer network device according to claim 133, wherein the digital adaptive equalizer comprises a feed forward equalizer, a three-level data slicer and a decision feedback equalizer.
 135. The computer network device according to claim 134, wherein the digital adaptive equalizer comprises an adder that has a first input, a second input and an output, wherein the first input is coupled to the feed forward equalizer, wherein the second input is coupled to the decision feedback equalizer and wherein the output is coupled to the three-level data slicer.
 136. The computer network device according to claim 134, wherein first receiver and equalizer comprises timing recovery circuitry, wherein timing recover circuitry comprises a low gain error generator, a high gain error generator, a loop filter, a phase inverter and a controller. 